From d6e399973e9bc6447a28b80cacffcbc6a768f1ed Mon Sep 17 00:00:00 2001 From: thajohns Date: Thu, 9 Sep 2021 01:15:22 -0400 Subject: got pre-linking steps working, removed glob includes --- src/synth/rel.rs | 39 +++++++++++++++++++++++---------------- 1 file changed, 23 insertions(+), 16 deletions(-) (limited to 'src/synth/rel.rs') diff --git a/src/synth/rel.rs b/src/synth/rel.rs index d2fbb70..93b0cd1 100644 --- a/src/synth/rel.rs +++ b/src/synth/rel.rs @@ -1,5 +1,8 @@ +use super::{ + FactoryParameters, GenBox, GenFactoryError, Generator, GeneratorFactory, ParamKind, ParamValue, + Parameters, Rate, SampleBuffer, +}; use std::{cmp, mem}; -use super::*; #[derive(Debug)] pub enum RelOp { @@ -97,28 +100,32 @@ impl Generator for Rel { 0.0 }; } - }, + } Rate::Control => { let val = left_buf.first(); let thres = right_buf.first(); - self.buf.set(if match self.op { - RelOp::Greater => val > thres, - RelOp::GreaterEqual => val >= thres, - RelOp::Equal => val == thres, - RelOp::NotEqual => val != thres, - RelOp::LessEqual => val <= thres, - RelOp::Less => val < thres, - } { - 1.0 - } else { - 0.0 - }); - }, + self.buf.set( + if match self.op { + RelOp::Greater => val > thres, + RelOp::GreaterEqual => val >= thres, + RelOp::Equal => val == thres, + RelOp::NotEqual => val != thres, + RelOp::LessEqual => val <= thres, + RelOp::Less => val < thres, + } { + 1.0 + } else { + 0.0 + }, + ); + } } &self.buf } - fn buffer(&self) -> &SampleBuffer { &self.buf } + fn buffer(&self) -> &SampleBuffer { + &self.buf + } fn set_buffer(&mut self, buf: SampleBuffer) -> SampleBuffer { mem::replace(&mut self.buf, buf) } -- cgit v1.2.3-70-g09d2